Synopsys, Inc. is the largest vender of Electronic Design Automation (EDA) software in the world.

Our LVS (Layout versus Schematic) QA group is now hiring students for intern positions.
The candidates must be able to work for at least 3 days per week from this March to June.

Qualification & requirements:
1. Technical requirement:
- Strong technical expertise in Unix-like operation systems.
- Strong knowledge in scripting language like Perl
- Knowledge of different netlist format such as Verilog,Spice is a plus
2. Key Soft skill:
- English communication;
- Commitment and responsiveness;
Student in graduate school (Marsters degree candidate in 1st or 2nd yr) is prefered.

Responsibilities:
(1) Parse the layout netlist file, and generate a connectivity network for the design
(2) Modify the connectivity network according to the different debug messages.
(3) Generate a new layout netlist file after the modification
(4) Run LVS and generate a report about the compare result
(5) Set up regression and webpage report system

實(shí)習(xí)薪水貌似不錯(cuò)
有興趣的童鞋可以聯(lián)系：
jjxu@synopsys.com